Decoder hardware comparator

Created on November 04, 2026 by Marwan Jalaleddine

2026   ·   hardware   vlsi   decoders   ldpc   polar-codes   grand   tools   ·   tools

Hardware papers on channel decoders report throughput, area and energy, while the error-correction performance usually sits in a different figure, for a different code, or in another paper. This page puts the two side by side. Pick any two hardware metrics for the scatter plot, click designs to select them, and their frame error rate (FER) curves appear in the plot on the right.

The table collects the implementations I track for my own work: LDPC, polar SC and SCL, automorphism ensemble decoders, GRAND, and product codes. Every number comes from the paper linked in the last column. I add designs and simulation results as they become available.

Hardware

Error-rate performance

    Metrics and scaling rules

    For a design with throughput \(T\) (Gb/s), area \(A\) (mm²) and power \(P\) (mW), built in node \(n_1\) at supply \(V_1\):

    $$\mathrm{AE} = \frac{T}{A}\ \left[\tfrac{\mathrm{Gb/s}}{\mathrm{mm}^2}\right], \qquad \mathrm{EE} = \frac{P}{T}\ \left[\tfrac{\mathrm{pJ}}{\mathrm{bit}}\right]$$

    Scaling to node \(n_2\) and supply \(V_2\) uses the area and energy factors

    $$S_A = \left(\frac{n_2}{n_1}\right)^{2}, \qquad S_E = \left(\frac{V_2}{V_1}\right)^{2}\left(\frac{n_2}{n_1}\right)^{2}$$

    so that

    $$A' = S_A\,A, \qquad \mathrm{AE}' = \frac{\mathrm{AE}}{S_A}, \qquad \mathrm{EE}' = S_E\,\mathrm{EE}, \qquad P' = S_E\,P, \qquad T' = T.$$

    Throughput is not scaled. Energy needs \(V_1\), so designs without a reported supply voltage drop out of energy and power plots while scaling is on. These are first-order CMOS rules (C.-H. Lin et al., IEEE TCAS-I, 2009). Treat scaled values as rough estimates.

    Diamonds have a full FER curve. When only the Eb/N0 at FER = 10-5 is known, it is drawn as a cross. Each selected design gets a card under the plots with its full details and notes, and the last column of the table holds the notes too (click a note to expand it). The page address keeps your selection, so you can share a comparison.

    Reading the numbers

    • Throughput is what each paper reports. Some papers give coded throughput and others give information throughput, so check the hover text before comparing a pair closely. For GRAND decoders, throughput is the average at the operating point. The worst case is in the notes.
    • Area efficiency is throughput divided by area, and energy efficiency is power divided by throughput (pJ per bit). Where a paper does not report one of them, it is computed from the other columns.
    • Scaling follows the first-order CMOS rules written out in “Metrics and scaling rules” above the table. Throughput is not scaled, and designs without a reported supply voltage drop out of the energy plots when scaling is on. Treat scaled numbers as rough estimates.
    • Error-rate curves are my own AFF3CT simulations: BPSK over AWGN, at least 100 frame errors per point (except the last point of some curves). A solid curve runs the same code, algorithm and quantization as the paper. A dashed curve is an approximation (for example a different quantization, construction or iteration count); the reason is shown on hover, and the paper’s own FER 1e-5 point is drawn as a cross next to it when the paper reports one. You can add any curve by hand from the “Add simulated curves” list.
    • Area can come from synthesis, place and route, or a fabricated chip. These are not equivalent, and the type is listed where I know it.

    If you spot a wrong number or want a design added, send me an email.