I am a PhD candidate in Electrical Engineering at McGill University, where I work in the Integrated Systems for Information Processing (ISIP) Lab under the supervision of Prof. Warren J. Gross. My research is on modern error-correcting codes for 5G and 6G communication systems.
My work spans guessing random additive noise decoding (GRAND), ordered statistics decoding, polar codes, optimization-based decoders, and machine learning decoders, with an emphasis on algorithms that map well to efficient hardware. I co-authored the Springer book Guessing Random Additive Noise Decoding: A Hardware Perspective, and I have been a teaching assistant for computer organization and digital systems courses at McGill since 2020.
I am looking for industry or academic positions starting in 2027 in channel coding, digital communications, decoder hardware, and machine learning for communications.
Research
Universal decoding (GRAND & OSD)
Code-agnostic decoders that guess the noise rather than the codeword, including GRAND variants and partial ordered statistics decoding with better error patterns.
Polar codes & HARQ
Successive-cancellation and list decoders for polar codes, and making incremental-redundancy HARQ practical for them.
Decoder hardware (VLSI)
High-throughput, energy-efficient decoder architectures, from algorithm–hardware co-design to ASIC and FPGA results.
Optimization-based decoding
Casting decoding as an optimization problem, using QUBO formulations and simulated annealing.
News
| Nov 04, 2025 | US patent granted: “Polar decoder and associated method” (US 12,463,747 B2), an optimization-based polar decoder developed with Huayi Zhou, Ryan Seah, and Warren J. Gross. |
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| Jun 01, 2025 | Paper accepted at ICC 2025: “Hardware-friendly IR-HARQ for Polar SCL Decoders” |
| Sep 15, 2024 | Published in IEEE TCOMM: “Reduced-Complexity Projection-Aggregation List Decoder for Reed-Muller Codes” |
| Jul 01, 2024 | Published in IEEE JSAC: “Decoding of Polar Codes Using Quadratic Unconstrained Binary Optimization” |
Compare decoders
Pick decoders and a code to compare frame error rate against area, throughput and energy, scaled to a common technology node.
Add simulated curves (), grouped by code
Metrics and scaling rules
For a design with throughput \(T\) (Gb/s), area \(A\) (mm²) and power \(P\) (mW), built in node \(n_1\) at supply \(V_1\):
$$\mathrm{AE} = \frac{T}{A}\ \left[\tfrac{\mathrm{Gb/s}}{\mathrm{mm}^2}\right], \qquad \mathrm{EE} = \frac{P}{T}\ \left[\tfrac{\mathrm{pJ}}{\mathrm{bit}}\right]$$Scaling to node \(n_2\) and supply \(V_2\) uses the area and energy factors
$$S_A = \left(\frac{n_2}{n_1}\right)^{2}, \qquad S_E = \left(\frac{V_2}{V_1}\right)^{2}\left(\frac{n_2}{n_1}\right)^{2}$$so that
$$A' = S_A\,A, \qquad \mathrm{AE}' = \frac{\mathrm{AE}}{S_A}, \qquad \mathrm{EE}' = S_E\,\mathrm{EE}, \qquad P' = S_E\,P, \qquad T' = T.$$Throughput is not scaled. Energy needs \(V_1\), so designs without a reported supply voltage drop out of energy and power plots while scaling is on. These are first-order CMOS rules (C.-H. Lin et al., IEEE TCAS-I, 2009). Treat scaled values as rough estimates.
Diamonds have a full FER curve. When only the Eb/N0 at FER = 10-5 is known, it is drawn as a cross. Each selected design gets a card under the plots with its full details and notes, and the last column of the table holds the notes too (click a note to expand it). The page address keeps your selection, so you can share a comparison.