Montreal, 2026

Hi, I'm Marwan.

I'm a PhD candidate at McGill University. I design the decoders that repair wireless signals after noise has scrambled them, and the chips that run them. Scroll to send a message from Beirut to Montreal and see how it gets through.

Beirut · 2015 to 2019

Where the message starts

I studied Electrical and Computer Engineering at the American University of Beirut and graduated with High Distinction. Along the way I helped run the robotics club's regional design challenge and TEDxAUB, and worked on street lighting for a village in south Lebanon.

Montreal · 2019 to now

A long way north

I came to McGill for a master's, then stayed for a PhD in Prof. Warren Gross's Integrated Systems for Information Processing Lab. Winters are long, which is good for writing papers.

The problem

Every channel is noisy

On the way, interference and fading flip bits. A 1 leaves the transmitter and a 0 arrives. Error-correcting codes add a little structure to every message so that the receiver can work out what was sent anyway.

Research · universal decoding

Guess the noise, not the message

Guessing random additive noise decoding (GRAND) tries the most likely noise patterns first and stops as soon as one gives a valid codeword. It works with any code. I co-wrote the Springer book on building it in hardware, and I also work on ordered statistics decoding.

Read the book

Research · polar codes and HARQ

Bridges made of butterflies

Polar codes protect the control channels of 5G. My recent work lets fast successive-cancellation and list decoders handle incremental-redundancy HARQ, so a failed packet can be fixed by sending a few more bits instead of the whole thing again.

See the papers

Research · decoder hardware

It has to fit on a chip

An algorithm only matters if it can run at gigabits per second on a few square millimetres of silicon. I design decoder architectures for ASICs and FPGAs, and I co-invented an optimization-based polar decoder (US Patent 12,463,747).

Compare decoders below

McGill · since 2020

Passing it on

I run the labs and tutorials for Computer Organization and Digital Systems, where students write ARM assembly and build hardware on FPGA boards. Across 370 course evaluations, students rate my help with the material at 4.2 out of 5.

Teaching evaluations

Message received · 0 errors

Let's work together

I'm looking for industry or academic positions starting in 2027 in channel coding, digital communications, decoder hardware and machine learning for communications.

Skip the ride

Play

Decoder playground

Pick decoders and a code to compare frame error rate against area, throughput and energy, scaled to a common technology node.

Hardware

Error-rate performance

    Metrics and scaling rules

    For a design with throughput \(T\) (Gb/s), area \(A\) (mm²) and power \(P\) (mW), built in node \(n_1\) at supply \(V_1\):

    $$\mathrm{AE} = \frac{T}{A}\ \left[\tfrac{\mathrm{Gb/s}}{\mathrm{mm}^2}\right], \qquad \mathrm{EE} = \frac{P}{T}\ \left[\tfrac{\mathrm{pJ}}{\mathrm{bit}}\right]$$

    Scaling to node \(n_2\) and supply \(V_2\) uses the area and energy factors

    $$S_A = \left(\frac{n_2}{n_1}\right)^{2}, \qquad S_E = \left(\frac{V_2}{V_1}\right)^{2}\left(\frac{n_2}{n_1}\right)^{2}$$

    so that

    $$A' = S_A\,A, \qquad \mathrm{AE}' = \frac{\mathrm{AE}}{S_A}, \qquad \mathrm{EE}' = S_E\,\mathrm{EE}, \qquad P' = S_E\,P, \qquad T' = T.$$

    Throughput is not scaled. Energy needs \(V_1\), so designs without a reported supply voltage drop out of energy and power plots while scaling is on. These are first-order CMOS rules (C.-H. Lin et al., IEEE TCAS-I, 2009). Treat scaled values as rough estimates.

    Diamonds have a full FER curve. When only the Eb/N0 at FER = 10-5 is known, it is drawn as a cross. Each selected design gets a card under the plots with its full details and notes, and the last column of the table holds the notes too (click a note to expand it). The page address keeps your selection, so you can share a comparison.

    Read

    Selected papers

    1. Preprint
      A Universal Systematic Method to Generate Error Patterns on Memoryless Channels
      Marwan Jalaleddine, Jiajie Li, Syed Mohsin Abbas, and Warren J Gross
      2026
    2. COMML
      Enabling Fast Polar SC Decoding with IR-HARQ
      Marwan Jalaleddine, Mohamad Ali Jarkas, Jiajie Li, and Warren J Gross
      IEEE Communications Letters, 2026
    3. ICC
      Hardware-friendly IR-HARQ for Polar SCL Decoders
      Marwan Jalaleddine, Jiajie Li, and Warren J Gross
      In 2025 IEEE International Conference on Communications, 2025
    4. ISIT
      Partial Ordered Statistics Decoding with Enhanced Error Patterns
      Marwan Jalaleddine, Huayi Zhou, Jiajie Li, and Warren J Gross
      In IEEE International Symposium on Information Theory, 2023
    All publications

    Lately

    News

    Nov 04, 2025 US patent granted: “Polar decoder and associated method” (US 12,463,747 B2), an optimization-based polar decoder developed with Huayi Zhou, Ryan Seah, and Warren J. Gross.
    Jun 01, 2025 Paper accepted at ICC 2025: “Hardware-friendly IR-HARQ for Polar SCL Decoders”
    Sep 15, 2024 Published in IEEE TCOMM: “Reduced-Complexity Projection-Aggregation List Decoder for Reed-Muller Codes”
    Jul 01, 2024 Published in IEEE JSAC: “Decoding of Polar Codes Using Quadratic Unconstrained Binary Optimization”