Hardware Metrics Scaling Calculator

• Area Efficiency: $\text{AE} = \frac{\text{Throughput (Gbps)}}{\text{Area (mm}^2\text{)}}$ (Gbps/mm²)
• Energy Efficiency: $\text{EE} = \frac{\text{Power (mW)}}{\text{Throughput (Gbps)}}$ (pJ/bit)
• Dynamic Power: $P \approx C \times V_{DD}^2 \times f$ (dynamic power)
• Throughput: $\frac{\text{Code Length (bits)}}{\text{Time for a new output to appear (ns)}}$ (Gbps)
• Information Throughput: $\frac{\text{Message Length (bits)}}{\text{Time for a new output to appear (ns)}}$ (Gbps)

Typical scaling from node size $n_1$ to $n_2$ with voltage $V_1$ to $V_2$:

• Area Factor: $AS = \left(\frac{n_2}{n_1}\right)^2$
• Energy Factor: $ES=\left (\frac{V_2}{ V_1} \right)^2 \times \left( \frac{n_2}{n_1}\right)^2$
• Scaled Area Efficiency: $\text{AE}_{scaled} = \frac{\text{Throughput (Gbps)}}{\text{Area (mm}^2\text{)} \times AS}$ (Gbps/mm²)
• Scaled Energy Efficiency: $\text{EE}_{scaled} = ES \times \frac{\text{Power (mW)}}{\text{Throughput (Gbps)}}$ (pJ/bit)

Note: Actual scaling depends on design, architecture, and process variations. Scaling parameters obtained from: C. -H. Lin, C. -Y. Chen, A. -Y. Wu and T. -H. Tsai, "Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 1005-1016, May 2009, doi: 10.1109/TCSI.2009.2017118.

Select target technology nodes to estimate scaled performance:

• Simplified Model: This calculator uses simplified CMOS scaling rules. Real designs face more complex tradeoffs.
• Architecture Impact: Scaling may enable architectural changes (more parallelism, pipelining) not captured here.
• Leakage Power: Static power becomes dominant at smaller nodes and is not fully modeled.
• Design Complexity: Smaller nodes often require more sophisticated design techniques.

• 180nm: ~1.8V, legacy designs
• 90nm: ~1.2V, mature process
• 65nm: ~1.1V
• 45nm: ~1.0V
• 28nm: ~0.9V, widely used
• 16nm/14nm: ~0.8V, FinFET
• 7nm: ~0.75V, advanced FinFET
• 5nm: ~0.7V, leading edge
• 3nm: ~0.65V, cutting edge